SPMCK16Z4MPV20 datasheet(424/500 Pages) FREESCALE

424 / 500 page

M68HC16 Z SERIES

D-50

USER’S MANUAL

SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt

enable bit. SPCR2 is buffered. New SPCR2 values become effective only after com-

pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to

restart at the designated location. Reads of SPCR2 return the value of the register, not

the buffer.

SPIFIE — SPI Finished Interrupt Enable

0 = QSPI interrupts disabled.

1 = QSPI interrupts enabled.

WREN — Wrap Enable

0 = Wraparound mode disabled.

1 = Wraparound mode enabled.

WRTO — Wrap To

0 = Wrap to pointer address $0.

1 = Wrap to address in NEWQP.

Bit 12 — Not Implemented

ENDQP[3:0] — Ending Queue Pointer

This field contains the last QSPI queue address.

Bits [7:4] — Not Implemented

NEWQP[3:0] — New Queue Pointer Value

This field contains the first QSPI queue address.

D.6.13 QSPI Control Register 3

SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and

the halt control bit. SPCR3 must be initialized before QSPI operation begins. Writing

a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains

information concerning the current serial transmission.

Bits [15:11] — Not Implemented

LOOPQ — QSPI Loop Mode

0 = Feedback path disabled.

1 = Feedback path enabled.

LOOPQ controls feedback on the data serializer for testing.

SPCR3 — QSPI Control Register

$YFFC1E

SPSR — QSPI Status Register

$YFFC1F

NOT USED

LOOPQ

HMIE

HALT

SPIF

MODF

HALTA

NOT

USED

CPTQP[3:0]

RESET:

Freescale Semiconductor, Inc.

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