SPMCK16Z4MPV20 datasheet(425/500 Pages) FREESCALE

425 / 500 page

M68HC16 Z SERIES

USER’S MANUAL

D-51

HMIE — HALTA and MODF Interrupt Enable

0 = HALTA and MODF interrupts disabled.

1 = HALTA and MODF interrupts enabled.

HMIE enables interrupt requests generated by the HALTA status flag or the MODF

status flag in SPSR.

HALT — Halt QSPI

0 = QSPI operates normally.

1 = QSPI is halted for subsequent restart.

When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state

from which it can later be restarted.

SPIF — QSPI Finished Flag

0 = QSPI is not finished.

1 = QSPI is finished.

SPIF is set after execution of the command at the address in ENDQP[3:0].

MODF — Mode Fault Flag

0 = Normal operation.

1 = Another SPI node requested to become the network SPI master while the QSPI

was enabled in master mode.

The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS

input pin is negated by an external driver.

HALTA — Halt Acknowledge Flag

0 = QSPI is not halted.

1 = QSPI is halted.

HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit.

Bit 4 — Not Implemented

CPTQP[3:0] — Completed Queue Pointer

CPTQP[3:0] points to the last command executed. It is updated when the current com-

mand is complete. When the first command in a queue is executing, CPTQP[3:0] con-

tains either the reset value $0 or a pointer to the last command completed in the

previous queue.

D.6.14 Receive Data RAM

RR[0:F] — Receive Data RAM

$YFFD00 – $YFFD1F

Data received by the QSPI is stored in this segment. The CPU16 reads this segment

to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused

bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-

vidual queue entry. Receive RAM data can be accessed using byte, word, or long-

word addressing.

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