SPMCK16Z4MPV20 datasheet(421/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-47

WOMQ — Wired-OR Mode for QSPI Pins

0 = Pins designated for output by DDRQS operate in normal mode.

1 = Pins designated for output by DDRQS operate in open-drain mode.

BITS[3:0] — Bits Per Transfer

In master mode, when BITSE is set in a command RAM byte, BITS[3:0] determines

the number of data bits transferred. When BITSE is cleared, eight bits are transferred.

Reserved values default to eight bits. In slave mode, the command RAM is not used

and the setting of BITSE has no effect on QSPI transfers. Instead, the BITS[3:0] field

determines the number of bits the QSPI will receive during each transfer before storing

the received data.

Table D-35 shows the number of bits per transfer.

CPOL — Clock Polarity

0 = The inactive state of SCK is logic zero.

1 = The inactive state of SCK is logic one.

CPOL is used to determine the inactive state of the serial clock (SCK). It is used with

CPHA to produce a desired clock/data relationship between master and slave devices.

CPHA — Clock Phase

0 = Data is captured on the leading edge of SCK and changed on the trailing edge

of SCK.

1 = Data is changed on the leading edge of SCK and captured on the trailing edge

of SCK

CPHA determines which edge of SCK causes data to change and which edge causes

data to be captured. CPHA is used with CPOL to produce a desired clock/data rela-

tionship between master and slave devices.

Table D-35 Bits Per Transfer

BITS[3:0]

Bits Per Transfer

0000

0001

Reserved

0010

Reserved

0011

Reserved

0100

Reserved

0101

Reserved

0110

Reserved

0111

Reserved

1000

1001

1010

1011

1100

1101

1110

1111

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