SPMCK16Z4MPV20 datasheet(444/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-70

USER’S MANUAL

OC1M[5:1] — OC1 Mask Field

OC1M[5:1] correspond to OC[5:1].

0 = Corresponding output compare pin is not affected by OC1 compare.

1 = Corresponding output compare pin is affected by OC1 compare.

OC1D[5:1] — OC1 Data Field

OC1D[5:1] correspond to OC[5:1].

0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1

match.

1 = If OC1 mask bit is set, the set corresponding output compare pin on OC1

match.

D.8.6 Timer Counter Register

TCNT — Timer Counter Register

$YFF90A

TCNT is the 16-bit free-running counter associated with the input capture, output com-

pare, and pulse accumulator functions of the GPT module.

D.8.7 Pulse Accumulator Control Register/Counter

PACTL enables the pulse accumulator and selects either event counting or gated

mode. In event counting mode, PACNT is incremented each time an event occurs. In

gated mode, it is incremented by an internal clock.

PAIS — PAI Pin State (Read Only)

PAEN — Pulse Accumulator Enable

0 = Pulse accumulator disabled.

1 = Pulse accumulator enabled.

PAMOD — Pulse Accumulator Mode

0 = External event counting.

1 = Gated time accumulation.

PEDGE — Pulse Accumulator Edge Control

The effects of PAMOD and PEDGE are shown in Table D-44.

PACTL/PACNT — Pulse Accumulator Control Register/Counter

$YFF90C

PAIS

PAEN

PAMOD PEDGE PCLKS

I4/O5

PACLK[1:0]

PULSE ACCUMULATOR COUNTER

RESET:

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