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SPMCK16Z4MPV20 Datasheet(PDF) 446 Page - Freescale Semiconductor, Inc

Part # SPMCK16Z4MPV20
Description  M68HC16Z Series
PDF  500 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

SPMCK16Z4MPV20 Datasheet(HTML) 446 Page - Freescale Semiconductor, Inc

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REGISTER SUMMARY
M68HC16 Z SERIES
D-72
USER’S MANUAL
D.8.10 Input Capture 4/Output Compare 5 Register
TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, de-
pending on the state of I4/O5 in PACTL. It is reset to $FFFF.
D.8.11 Timer Control Registers 1 and 2
TCTL1 determines output compare mode and output logic level. TCTL2 determines
the type of input capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful.
Refer to Table D-46.
EDGE[4:1] — Input Capture Edge Control
Each pair of bits configures input sensing logic for the corresponding input capture.
Refer to Table D-47.
D.8.12 Timer Interrupt Mask Registers 1 and 2
TCTL1/TCTL2 — Timer Control Registers 1–2
$YFF91E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table D-46 OM/OL[5:2] Effects
OM/OL[5:2]
Action Taken
00
Timer disconnected from output logic
01
Toggle OCx output line
10
Clear OCx output line to zero
11
Set OCx output line to one
Table D-47 EDGE[4:1] Effects
EDGE[4:1]
Configuration
00
Capture disabled
01
Capture on rising edge only
10
Capture on falling edge only
11
Capture on any (rising or falling) edge
TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2
$YFF920
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I4/O5I
OCI[4:1]
ICI[3:1]
TOI
0
PAOVI
PAII
CPROUT
CPR[2:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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