SPMCK16Z4MPV20 datasheet(155/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-49

Internal single byte or aligned word writes are guaranteed valid for synchronous re-

sets. External writes are also guaranteed to complete, provided the external configu-

ration logic on the data bus is conditioned as shown in Figure 5-18.

5.7.3 Reset Mode Selection

The logic states of certain data bus pins during reset determine SIM operating config-

uration. In addition, the state of the MODCLK pin determines system clock source and

the state of the BKPT pin determines what happens during subsequent breakpoint as-

sertions. Table 5-19 is a summary of reset mode selection options.

Table 5-18 Reset Source Summary

Type

Source

Timing

Cause

Reset Lines Asserted by

Controller

External

Synch

RESET pin

MSTRST

CLKRST

EXTRST

Power up

EBI

Asynch

VDD

MSTRST

CLKRST

EXTRST

Software watchdog

Monitor

Asynch

Time out

MSTRST

CLKRST

EXTRST

HALT

Monitor

Asynch

Internal HALT assertion

(e.g. double bus fault)

MSTRST

CLKRST

EXTRST

Loss of clock

Clock

Synch

Loss of reference

MSTRST

CLKRST

EXTRST

Test

Synch

Test mode

MSTRST

—

EXTRST

Table 5-19 Reset Mode Selection

Mode Select Pin

Default Function

(Pin Left High)

Alternate Function

(Pin Pulled Low)

DATA0

CSBOOT 16-Bit

CSBOOT 8-Bit

DATA1

CS0

CS1

CS2

BGACK

DATA2

CS3

CS4

CS5

FC0

FC1

FC2

DATA3

DATA4

DATA5

DATA6

DATA7

CS6

CS[7:6]

CS[8:6]

CS[9:6]

CS[10:6]

ADDR19

ADDR[20:19]

ADDR[21:19]

ADDR[22:19]

ADDR[23:19]

DATA8

DSACK[1:0],

AVEC, DS, AS,

SIZ[1:0]

PORTE

DATA9

IRQ[7:1]

MODCLK

PORTF

DATA11

Normal Operation1

NOTES:

1. DATA11 must remain high during reset to ensure normal operation.

Reserved

MODCLK

VCO = System Clock

EXTAL = System Clock

BKPT

Background Mode Disabled

Background Mode Enabled

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SPMCK16Z4MPV20 Datasheet(PDF) 155 Page - Freescale Semiconductor, Inc

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