SPMCK16Z4MPV20 datasheet(152/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-46

USER’S MANUAL

The halt operation has no effect on bus arbitration. However, when external bus arbi-

tration occurs while the MCU is halted, address and control signals go into a high-im-

pedance state. If HALT is still asserted when the MCU regains control of the bus,

address, function code, size, and read/write signals revert to the previous driven

states. The MCU cannot service interrupt requests while halted.

5.6.6 External Bus Arbitration

The MCU bus design provides for a single bus master at any one time. Either the MCU

or an external device can be master. Bus arbitration protocols determine when an ex-

ternal device can become bus master. Bus arbitration requests are recognized during

normal processing, HALT assertion, and when the CPU has halted due to a double

bus fault.

The bus controller in the MCU manages bus arbitration signals so that the MCU has

the lowest priority. External devices that need to obtain the bus must assert bus arbi-

tration signals in the sequences described in the following paragraphs.

Systems that include several devices that can become bus master require external cir-

cuitry to assign priorities to the devices, so that when two or more external devices at-

tempt to become bus master at the same time, the one having the highest priority

becomes bus master first. The protocol sequence is:

1. An external device asserts the bus request signal (BR).

2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available.

3. An external device asserts the bus grant acknowledge (BGACK) signal to indi-

cate that it has assumed bus mastership.

BR can be asserted during a bus cycle or between cycles. BG is asserted in response

to BR. To guarantee operand coherency, BG is only asserted at the end of operand

transfer.

If more than one external device can be bus master, required external arbitration must

begin when a requesting device receives BG. An external device must assert BGACK

when it assumes mastership, and must maintain BGACK assertion as long as it is bus

master.

Two conditions must be met for an external device to assume bus mastership. The de-

vice must receive BG through the arbitration process, and BGACK must be inactive,

indicating that no other bus master is active. This technique allows the processing of

bus requests during data transfer cycles.

BG is negated a few clock cycles after BGACK transition. However, if bus requests are

still pending after BG is negated, the MCU asserts BG again within a few clock cycles.

This additional BG assertion allows external arbitration circuitry to select the next bus

master before the current master has released the bus.

Refer to Figure 5-17, which shows bus arbitration for a single device. The flowchart

shows BR negated at the same time BGACK is asserted.

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SPMCK16Z4MPV20 Datasheet(PDF) 152 Page - Freescale Semiconductor, Inc

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