SPMCK16Z4MPV20 datasheet(153/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-47

Figure 5-17 Bus Arbitration Flowchart for Single Request

5.6.6.1 Show Cycles

The MCU normally performs internal data transfers without affecting the external bus,

but it is possible to show these transfers during debugging. AS is not asserted exter-

nally during show cycles.

Show cycles are controlled by the SHEN[1:0] in SIMCR. This field is set to %00 by re-

set. When show cycles are disabled, the address bus, function codes, size, and read/

write signals reflect internal bus activity, but AS and DS are not asserted externally and

external data bus pins are in high-impedance state during internal accesses. Refer to

5.2.3 Show Internal Cycles and the

SIM Reference Manual (SIMRM/AD) for more

information.

When show cycles are enabled, DS is asserted externally during internal cycles, and

internal data is driven out on the external data bus. Because internal cycles normally

continue to run when the external bus is granted, one SHEN[1:0] encoding halts inter-

nal bus activity while there is an external master.

SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion

of the data bus is valid during the cycle. During a byte write to an internal address, the

portion of the bus that represents the byte that is not written reflects internal bus con-

ditions, and is indeterminate. During a byte write to an external address, the data mul-

tiplexer in the SIM causes the value of the byte that is written to be driven out on both

bytes of the data bus.

GRANT BUS ARBITRATION

1) ASSERT BUS GRANT (BG)

TERMINATE ARBITRATION

1) NEGATE BG (AND WAIT FOR

BGACK TO BE NEGATED)

RE-ARBITRATE OR RESUME PROCESSOR

OPERATION

MCU

REQUESTING DEVICE

REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

ACKNOWLEDGE BUS MASTERSHIP

1) EXTERNAL ARBITRATION DETERMINES

NEXT BUS MASTER

2) NEXT BUS MASTER WAITS FOR BGACK

TO BE NEGATED

3) NEXT BUS MASTER ASSERTS BGACK

TO BECOME NEW MASTER

4) BUS MASTER NEGATES BR

OPERATE AS BUS MASTER

1) PERFORM DATA TRANSFERS (READ AND

WRITE CYCLES) ACCORDING TO THE SAME

RULES THE PROCESSOR USES

RELEASE BUS MASTERSHIP

1) NEGATE BGACK

BUS ARB FLOW

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