SPMCK16Z4MPV20 datasheet(150/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-44

USER’S MANUAL

5.6.5.1 Bus Errors

The CPU16 treats bus errors as a type of exception. Bus error exception processing

begins when the CPU16 detects assertion of the IMB BERR signal.

BERR assertions do not force immediate exception processing. The signal is synchro-

nized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle

in which it was asserted. Because bus cycles can overlap instruction boundaries, bus

error exception processing may not occur at the end of the instruction in which the bus

cycle begins. Timing of BERR detection/acknowledge is dependent upon several

factors:

• Which bus cycle of an instruction is terminated by assertion of BERR.

• The number of bus cycles in the instruction during which BERR is asserted.

• The number of bus cycles in the instruction following the instruction in which

BERR is asserted.

• Whether BERR is asserted during a program space access or a data space

access.

Because of these factors, it is impossible to predict precisely how long after occur-

rence of a bus error the bus error exception is processed.

Table 5-17 DSACK, BERR, and HALT Assertion Results

Type of

Termination

Control

Signal

Asserted on Rising

Edge of State

Description

of Result

NOTES:

1. S = The number of current even bus state (for example, S2, S4, etc.)

S + 2

NORMAL

DSACK

BERR

HALT

NA3

2. A = Signal is asserted in this bus state.

3. NA = Signal is not asserted in this state.

RA4

4. RA = Signal was asserted in previous state and remains asserted in this state.

5. X = Don’t care

Normal cycle terminate and continue.

HALT

DSACK

BERR

HALT

A/RA

Normal cycle terminate and halt.

Continue when HALT is negated.

BUS ERROR

DSACK

BERR

HALT

NA/A

Terminate and take bus error exception.

BUS ERROR

DSACK

BERR

HALT

Terminate and take bus error exception.

BUS ERROR

DSACK

BERR

HALT

NA/A

A/S

Terminate and take bus error exception.

BUS ERROR

DSACK

BERR

HALT

Terminate and take bus error exception.

Freescale Semiconductor, Inc.

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