SPMCK16Z4MPV20 datasheet(146/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-40

USER’S MANUAL

Fast termination cycles use internal handshaking signals generated by the chip-select

logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.

When AS, DS, and R/W are valid, a peripheral device either places data on the bus

(read cycle) or latches data from the bus (write cycle). At the appropriate time, chip-

select logic asserts data size acknowledge signals.

The DSACK option fields in the chip-select option registers determine whether inter-

nally generated DSACK or externally generated DSACK is used. The external DSACK

lines are always active, regardless of the setting of the DSACK field in the chip-select

option registers. Thus, an external DSACK can always terminate a bus cycle. Holding

a DSACK line low will cause essentially all external bus cycles to be three-cycle (zero

wait states) accesses unless the chip-select option register specifies fast accesses.

NOTE

There are certain exceptions to the three-cycle rule when one or both

DSACK lines are asserted. Check the current device and mask set

errata for details.

For fast termination cycles, the fast termination encoding (%1110) must be used. Re-

fer to 5.9.1 Chip-Select Registers for information about fast termination setup.

To use fast termination, an external device must be fast enough to have data ready

within the specified setup time (for example, by the falling edge of S4). Refer to AP-

PENDIX A ELECTRICAL CHARACTERISTICS for information about fast termination

timing.

When fast termination is in use, DS is asserted during read cycles but not during write

cycles. The STRB field in the chip-select option register used must be programmed

with the address strobe encoding to assert the chip-select signal for a fast termination

write.

5.6.4 CPU Space Cycles

Function code signals FC[2:0] designate which of eight external address spaces is ac-

cessed during a bus cycle. Address space 7 is designated CPU space. CPU space is

used for control information not normally associated with read or write bus cycles.

Function codes are valid only while AS is asserted. Refer to 5.5.1.7 Function Codes

for more information on codes and encoding.

During a CPU space access, ADDR[19:16] are encoded to reflect the type of access

being made. Three encodings are used by the MCU, as shown in Figure 5-14. These

encodings represent breakpoint acknowledge (type $0) cycles, low power stop broad-

cast (type $3) cycles, and interrupt acknowledge (type $F) cycles. Type $0 and type

$3 cycles are discussed in the following paragraphs. Refer to 5.8 Interrupts for infor-

mation about interrupt acknowledge bus cycles.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 146 Page - Freescale Semiconductor, Inc

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