SPMCK16Z4MPV20 datasheet(142/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-36

USER’S MANUAL

5.6 Bus Operation

Internal microcontroller modules are typically accessed in two system clock cycles.

Regular external bus cycles use handshaking between the MCU and external periph-

erals to manage transfer size and data. These accesses take three system clock cy-

cles, with no wait states. During regular cycles, wait states can be inserted as needed

by bus control logic. Refer to 5.6.2 Regular Bus Cycle for more information.

Fast-termination cycles, which are two-cycle external accesses with no wait states,

use chip-select logic to generate handshaking signals internally. Refer to 5.6.3 Fast

Termination Cycles and 5.9 Chip-Selects for more information. Bus control signal

timing, as well as chip-select signal timing, are specified in APPENDIX A ELECTRI-

CAL CHARACTERISTICS. Refer to the

SIM Reference Manual (SIMRM/AD) for more

information about each type of bus cycle.

5.6.1 Synchronization to CLKOUT

External devices connected to the MCU bus can operate at a clock frequency different

from the frequencies of the MCU as long as the external devices satisfy the interface

signal timing constraints. Although bus cycles are classified as asynchronous, they are

interpreted relative to the MCU system clock output (CLKOUT).

Table 5-16 Operand Alignment

Current

Cycle

Transfer Case

SIZ1

SIZ0

ADDR0

DSACK1 DSACK0

DATA

[15:8]

DATA

[7:0]

Cycle

Byte to 8-bit port (even)

OP0

(OP0)1

NOTES:

1. Operands in parentheses are ignored by the CPU16 during read cycles.

—

Byte to 8-bit port (odd)

OP0

(OP0)

—

Byte to 16-bit port (even)

OP0

(OP0)

—

Byte to 16-bit port (odd)

(OP0)

OP0

—

Word to 8-bit port

(aligned)

OP0

(OP1)

Word to 8-bit port

(misaligned)

OP0

(OP0)

Word to 16-bit port

(aligned)

OP0

OP1

—

Word to 16-bit port

(misaligned)

(OP0)

OP0

Long word to 8-bit port

(aligned)

OP0

(OP1)

Long word to 8-bit port

(misaligned)2

2. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers.

OP0

(OP0)

Long word to 16-bit port

(aligned)

OP0

OP1

Long word to 16-bit port

(misaligned)2

(OP0)

OP0

Three byte to 8-bit port3

3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.

OP0

(OP0)

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