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SPMCK16Z4MPV20 Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 138 Page - Freescale Semiconductor, Inc |
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138 / 500 page ![]() SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5-32 USER’S MANUAL 5.5.1.5 Read/Write Signal The read/write signal (R/W) determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two consecutive write cycles. 5.5.1.6 Size Signals Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while AS is asserted. Table 5-13 shows SIZ0 and SIZ1 encoding. 5.5.1.7 Function Codes The CPU generates function code signals (FC[2:0]) to indicate the type of activity oc- curring on the data or address bus. These signals can be considered address exten- sions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle. Because the CPU16 always operates in supervisor mode (FC2 = 1), address spaces 0 to 3 are not used. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while AS is asserted. Table 5-14 shows address space encoding. 5.5.1.8 Data Size Acknowledge Signals During normal bus transfers, external devices assert the data size acknowledge sig- nals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig- nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer to 5.9 Chip-Selects for more information. Table 5-13 Size Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long Word Table 5-14 Address Space Encoding FC2 FC1 FC0 Address Space 1 0 0 Reserved 1 0 1 Data space 1 1 0 Program space 1 1 1 CPU space Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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