SPMCK16Z4MPV20 datasheet(139/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-33

5.5.1.9 Bus Error Signal

The bus error signal (BERR) is asserted when a bus cycle is not properly terminated

by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to

indicate a bus error condition, provided it meets the appropriate timing requirements.

Refer to 5.6.5 Bus Exception Control Cycles for more information.

The internal bus monitor can generate the BERR signal for internal-to-internal and in-

ternal-to-external transfers. In systems with an external bus master, the SIM bus mon-

itor must be disabled and external logic must be provided to drive the BERR pin,

because the internal BERR monitor has no information about transfers initiated by an

external bus master. Refer to 5.6.6 External Bus Arbitration for more information.

5.5.1.10 Halt Signal

The halt signal (HALT) can be asserted by an external device for debugging purposes

to cause single bus cycle operation or (in combination with BERR) a retry of a bus cy-

cle in error. The HALT signal affects external bus cycles only. As a result, a program

not requiring use of the external bus may continue executing, unaffected by the HALT

signal. When the MCU completes a bus cycle with the HALT signal asserted,

DATA[15:0] is placed in a high-impedance state and bus control signals are driven in-

active; the address, function code, size, and read/write signals remain in the same

state. If HALT is still asserted once bus mastership is returned to the MCU, the ad-

dress, function code, size, and read/write signals are again driven to their previous

states. The MCU does not service interrupt requests while it is halted. Refer to 5.6.5

Bus Exception Control Cycles for further information.

5.5.1.11 Autovector Signal

The autovector signal (AVEC) can be used to terminate external interrupt acknowledg-

ment cycles. Assertion of AVEC causes the CPU16 to generate vector numbers to lo-

cate an interrupt handler routine. If AVEC is continuously asserted, autovectors are

generated for all external interrupt requests. AVEC is ignored during all other bus cy-

cles. Refer to 5.8 Interrupts for more information. AVEC for external interrupt re-

quests can also be supplied internally by chip-select logic. Refer to 5.9 Chip-Selects

for more information. The autovector function is disabled when there is an external bus

master. Refer to 5.6.6 External Bus Arbitration for more information.

5.5.2 Dynamic Bus Sizing

The MCU dynamically interprets the port size of an addressed device during each bus

cycle, allowing operand transfers to or from 8-bit and 16-bit ports.

During a bus transfer cycle, an external device signals its port size and indicates com-

pletion of the bus cycle to the MCU through the use of the DSACK inputs, as shown in

Table 5-15. Chip-select logic can generate data size acknowledge signals for an ex-

ternal device. Refer to 5.9 Chip-Selects for more information.

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