SPMCK16Z4MPV20 datasheet(135/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-29

The PIRQL field is compared to the CPU16 interrupt priority mask to determine wheth-

er the interrupt is recognized. Table 5-12 shows PIRQL[2:0] priority values. Because

of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt

request of the same priority. The periodic timer continues to run when the interrupt is

disabled.

The PIV field contains the periodic interrupt vector. The vector is placed on the IMB

when an interrupt request is made. The vector number is used to calculate the address

of the appropriate exception vector in the exception vector table. The reset value of

the PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.

5.4.8 Low-Power STOP Operation

When the CPU16 executes the LPSTOP instruction, the current interrupt priority mask

is stored in the clock control logic, internal clocks are disabled according to the state

of the STSIM bit in the SYNCR, and the MCU enters low-power stop mode. The bus

monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power

stop.

During low-power stop mode, the clock input to the software watchdog timer is dis-

abled and the timer stops. The software watchdog begins to run again on the first rising

clock edge after low-power stop mode ends. The watchdog is not reset by low-power

stop mode. A service sequence must be performed to reset the timer.

The periodic interrupt timer does not respond to the LPSTOP instruction, but continues

to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with

a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external

interrupt request, can bring the MCU out of the low-power stop mode if it has a higher

priority than the interrupt mask value stored in the clock control logic when low-power

stop mode is initiated. LPSTOP can be terminated by a reset.

5.5 External Bus Interface

The external bus interface (EBI) transfers information between the internal MCU bus

and external devices. Figure 5-10 shows a basic system with external memory and

peripherals.

Table 5-12 Periodic Interrupt Priority

PIRQL[2:0]

Priority Level

000

Periodic Interrupt Disabled

001

Interrupt priority level 1

010

Interrupt priority level 2

011

Interrupt priority level 3

100

Interrupt priority level 4

101

Interrupt priority level 5

110

Interrupt priority level 6

111

Interrupt priority level 7

Freescale Semiconductor, Inc.

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