SPMCK16Z4MPV20 datasheet(132/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-26

USER’S MANUAL

Both writes must occur before time-out in the order listed. Any number of instructions

can be executed between the two writes.

Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the

software watchdog timing (SWT[1:0]) field in SYPCR.

SWP determines system clock prescaling for the watchdog timer and determines that

one of two options, either no prescaling or prescaling by a factor of 512, can be select-

ed. The value of SWP is affected by the state of the MODCLK pin during reset, as

shown in Table 5-9. System software can change SWP value.

SWT[1:0] selects the divide ratio used to establish the software watchdog time-out

period.

The following equation calculates the time-out period for a slow reference frequency,

where fref is equal to the EXTAL crystal frequency.

The following equation calculates the time-out period for a fast reference frequency,

where fref is equal to the EXTAL crystal frequency.

The following equation calculates the time-out period for an externally input clock fre-

quency on both slow and fast reference frequency devices, when fsys is equal to the

system clock frequency.

Table 5-10 shows the divide ratio for each combination of SWP and SWT[1:0] bits.

When SWT[1:0] are modified, a watchdog service sequence must be performed be-

fore the new time-out period can take effect.

Table 5-9 MODCLK Pin and SWP Bit During Reset

MODCLK

SWP

0 (External Clock)

1 (

÷ 512)

1 (Internal Clock)

0 (

÷ 1)

Time-Out Period

Divide Ratio Specified by SWP and SWT[1:0]

ref

------------------------------------------------------------------------------------------------------------------------

Time-Out Period

128

() Divide Ratio Specified by SWP and SWT[1:0]

(

)

ref

--------------------------------------------------------------------------------------------------------------------------------------------

Time-Out Period

Divide Ratio Specified by SWP and SWT[1:0]

sys

------------------------------------------------------------------------------------------------------------------------

Freescale Semiconductor, Inc.

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