SPMCK16Z4MPV20 datasheet(131/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-25

The monitor does not check DSACK response on the external bus unless the CPU16

initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-

nal to external bus cycles. If a system contains external bus masters, an external bus

monitor must be implemented and the internal-to-external bus monitor option must be

disabled.

When monitoring transfers to an 8-bit port, the bus monitor does not reset until both

byte accesses of a word transfer are completed. Monitor time-out period must be at

least twice the number of clocks that a single byte access requires.

5.4.3 Halt Monitor

The halt monitor responds to an assertion of the HALT signal on the internal bus,

caused by a double bus fault. A flag in the reset status register (RSR) can indicate that

the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by

the halt monitor enable (HME) bit in SYPCR. Refer to 5.6.5.2 Double Bus Faults for

more information.

5.4.4 Spurious Interrupt Monitor

During interrupt exception processing, the CPU16 normally acknowledges an interrupt

request, arbitrates among various sources of interrupt, recognizes the highest priority

source, and then acquires a vector or responds to a request for autovectoring. The

spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt

arbitration occurs during interrupt exception processing. The assertion of BERR caus-

es the CPU16 to load the spurious interrupt exception vector into the program counter.

The spurious interrupt monitor cannot be disabled. Refer to 5.8 Interrupts for further

information. For detailed information about interrupt exception processing, refer to

4.13 Exceptions.

5.4.5 Software Watchdog

The software watchdog is controlled by the software watchdog enable (SWE) bit in

SYPCR. When enabled, the watchdog requires that a service sequence be written to

the software watchdog service register (SWSR) on a periodic basis. If servicing does

not take place, the watchdog times out and asserts the RESET signal.

Each time the service sequence is written, the software watchdog timer restarts. The

sequence to restart the software watchdog consists of the following steps:

• Write $55 to SWSR.

• Write $AA to SWSR.

Table 5-8 Bus Monitor Period

BMT[1:0]

Bus Monitor Time-Out Period

64 system clocks

32 system clocks

16 system clocks

8 system clocks

Freescale Semiconductor, Inc.

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