SPMCK16Z4MPV20 datasheet(133/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-27

Figure 5-9 is a block diagram of the watchdog timer and the clock control for the pe-

riodic interrupt timer.

Figure 5-9 Periodic Interrupt Timer and Software Watchdog Timer

5.4.6 Periodic Interrupt Timer

The periodic interrupt timer (PIT) allows the generation of interrupts of specific priority

at predetermined intervals. This capability is often used to schedule control system

tasks that must be performed within time constraints. The timer consists of a prescaler,

a modulus counter, and registers that determine interrupt timing, priority and vector as-

signment. Refer to 4.13 Exceptions for further information about interrupt exception

processing.

Table 5-10 Software Watchdog Divide Ratio

SWP

SWT[1:0]

Divide Ratio

000

001

211

010

213

011

215

100

218

101

220

110

222

111

224

FREEZE

EXTAL

CRYSTAL

OSCILLATOR

1281

XTAL

MODCLK

29 PRESCALER

CLOCK

SELECT

CLOCK SELECT

AND DISABLE

SWP

PTP

(8-BIT MODULUS COUNTER)

PIT

INTERRUPT

(215 DIVIDER CHAIN — 4 TAPS)

PERIODIC INTERRUPT TIMER

PICR

PITR

SOFTWARE WATCHDOG TIMER

SWSR

LPSTOP

SWE

SWT1

SWT0

SOFTWARE

WATCHDOG

RESET

PIT WATCHDOG BLOCK 16

NOTES:

÷ 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR.

Freescale Semiconductor, Inc.

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