SPMCK16Z4MPV20 datasheet(141/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-35

5.5.3 Operand Alignment

The EBI data multiplexer establishes the necessary connections for different combi-

nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit

bus and routes them to their required positions. Positioning of bytes is determined by

the size and address outputs. SIZ1 and SIZ0 indicate the number of bytes remaining

to be transferred during the current bus cycle. The number of bytes transferred is equal

to or less than the size indicated by SIZ1 and SIZ0, depending on port width.

ADDR0 also affects the operation of the data multiplexer. During a bus transfer,

ADDR[23:1] indicate the word base address of the portion of the operand to be ac-

cessed, and ADDR0 indicates the byte offset from the base.

NOTE

ADDR[23:20] follow the state of ADDR19 in the MCU.

5.5.4 Misaligned Operands

The CPU16 uses a basic operand size of 16 bits. An operand is misaligned when it

overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0

= 0 (an even address), the address is on a word and byte boundary. When ADDR0 =

1 (an odd address), the address is on a byte boundary only. A byte operand is aligned

at any address; a word or long-word operand is misaligned at an odd address.

The largest amount of data that can be transferred by a single bus cycle is an aligned

word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-

icant operand word is transferred on the first bus cycle and the least significant oper-

and word is transferred on a following bus cycle.

The CPU16 can perform misaligned word transfers. This capability makes it compati-

ble with the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two

misaligned word transfers.

5.5.5 Operand Transfer Cases

Table 5-16 shows how operands are aligned for various types of transfers. OPn en-

tries are portions of a requested operand that are read or written during a bus cycle

and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 141 Page - Freescale Semiconductor, Inc