SPMCK16Z4MPV20 datasheet(140/500 Pages) FREESCALE

140 / 500 page

SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-34

USER’S MANUAL

If the CPU is executing an instruction that reads a long-word operand from a 16-bit

port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob-

tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read

cycles. The addressed device uses the DSACK signals to indicate the port width. For

instance, a 16-bit external device always returns DSACK for a 16-bit port (regardless

of whether the bus cycle is a byte or word operation).

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or

from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],

and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus

cycles needed to transfer data and ensures that the MCU transfers valid data.

The MCU always attempts to transfer the maximum amount of data on all bus cycles.

For a word operation, it is assumed that the port is 16 bits wide when the bus cycle

begins.

Operand bytes are designated as shown in Figure 5-11. OP[0:3] represent the order

of access. For instance, OP0 is the most significant byte of a long-word operand, and

is accessed first, while OP3, the least significant byte, is accessed last. The two bytes

of a word-length operand are OP0 (most significant) and OP1. The single byte of a

byte-length operand is OP0.

Figure 5-11 Operand Byte Order

Table 5-15 Effect of DSACK Signals

DSACK1

DSACK0

Result

Insert wait states in current bus cycle

Complete cycle — Data bus port size is eight bits

Complete cycle — Data bus port size is sixteen bits

Reserved

OP0

OPERAND BYTE ORDER

OP1

OP2

OP3

16 15

8 7

BYTE ORDER

OPERAND

LONG WORD

THREE BYTE

WORD

BYTE

OP2

OP1

OP0

OP1

OP0

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