DM3725 datasheet(134/268 Pages) TI

134 / 268 page

SWPS038-008

sys_xtalin

OSC0

OSC1

SWPS038-009

sys_32k

CK0

CK1

DM3730, DM3725

SPRS685 – AUGUST 2010

www.ti.com

Table 4-5 details the squarer input clock timing requirements.

Table 4-5. sys_xtalin Squarer Input Clock Timing Requirements—Bypass Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

OCS0

1 / tc(xtalin)

Frequency, sys_xtalin

12, 13, 16.8, 19.2, 26, or 38.4

MHz

OCS1

tw(xtalin)

Pulse duration, sys_xtalin low or high

0.45 * tc(xtalin)

0.55 * tc(xtalin)

tJ(xtalin)

Peak-to-peak jitter(1), sys_xtalin

X%(2) *

tc(xtalin) (3) -

200

tR(xtalin)

Rise time, sys_xtalin

tF(xtalin)

Fall time, sys_xtalin

tJ(xtalin)

Frequency stability, sys_xtalin

+/-50

ppm

(+/-5ppm)(4)

(1)

–

Peak-to-peak jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

–

The minimum value is the difference between the shortest measured clock period and the expected clock period Maximum and

minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period

(2) Depending on the internal system clock divider configuration (PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bit field), the sys_xtalin

input clock can be divided by 2 to provide the standard system clock (SYS_CLK) frequencies. For more information, see the Power,

Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4). In X%, X

represents then the internal system clock divider with following possible values: X = 1 or 2.

(3) tc(xtalin) is the sys_xtalin cycle time of the clock coming to sys_xtalin ball.

(4) ±50 ppm is the clock frequency stability/accuracy and ±5 ppm takes into account the aging effects.

Figure 4-3. sys_xtalin Squarer Input Clock

4.1.4

sys_32k CMOS Input Clock

Table 4-6 summarizes the electrical characteristics of the sys_32k input clock.

Table 4-6. sys_32k Input Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency, sys_32k

32.768

kHz

Input capacitance

1.6

Input resistance

106

Ω

Table 4-7 details the input requirements of the sys_32k input clock.

Table 4-7. sys_32k Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CK0

1 / tc(32k)

Frequency, sys_32k

32.768

kHz

tR(32k)

Rise time, sys_32k

tF(32k)

Fall time, sys_32k

tJ(32k)

Frequency stability, sys_32k

200

ppm

Figure 4-4. sys_32k Input Clock

134

Clock Specifications

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