DM3725 datasheet(135/268 Pages) TI

135 / 268 page

SWPS038-010

sys_altclk

ALT0

ALT1

DM3730, DM3725

www.ti.com

SPRS685 – AUGUST 2010

4.1.5

sys_altclk CMOS Input Clock

Table 4-8 summarizes the electrical characteristics of the sys_altclk input clock.

Table 4-8. sys_altclk Input Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency, sys_altclk

48 or 54

MHz

Input capacitance

1.6

Input resistance

106

Ω

Table 4-9 details the input requirements of the sys_altclk input clock.

Table 4-9. sys_altclk Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

ALT0

1 / tc(altclk)

Frequency, sys_altclk

48 or 54

MHz

ALT1

tw(altclk)

Pulse duration, sys_altclk low or high

0.49 * tc(altclk)

0.51 * tc(altclk)

tJ(altclk)

Peak-to-peak jitter(1), sys_altclk

-1%

tR(altclk)

Rise time, sys_altclk

tF(altclk)

Fall time, sys_altclk

tJ(altclk)

Frequency stability, sys_altclk

ppm

(1) Peak-to-peak jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

–

The minimum value is the difference between the shortest measured clock period and the expected clock period Maximum and

minimum are obtained on a statistical population of 300 period samples and expressed relative to the expected clock period

Figure 4-5. sys_altclk Input Clock

Clock Specifications

135

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