FIP4F8S datasheet(30/33 Pages) FUJI

30 / 33 page

AN-087E Rev.1.0

April-2011

FA5526/5527/5528/5536/5537/5538

Fuji Electric Co., Ltd.

http://www.fujielectric.co.jp/products/semiconductor/

(9) Over Temperature Protection as latch mode

for FA5526 / 27 / 28

Over Temperature Protection as latch mode can be

achieved by the circuit shown in Fig.39 for FA5526/27/28.

Here, a diode D1 connected to separated line from VCC

pin, because the start-up time of IC may become too long

when the circuit including a thermistor is connected to VCC

pin of IC directly.

Please note that the circuit shown in Fig. 39 can not be

used for FA5536/37/38, because FA5536/37/38 does not

include any latch function.

(10)

Prevention

malfunction

caused

negative voltage applied to pins

When a large negative voltage is applied to a pin, a

parasitic element in the IC may operate and cause a

malfunction. Be sure that voltage applied to a pin shall not

be -0.3V or less.

Voltage oscillation generated at turn-off of the MOSFET

may be applied to the OUT pin via the parasitic

capacitance of the MOSFET, resulting in the negative

voltage applied to the OUT pin.

In such a case, connect a Shottky diode between each

pin and GND. Forward voltage of the Shottky diode can

suppress negative voltage at each pin. Use a Shottky

diode with low forward voltage.

Fig.40 shows an example of a circuit with a Shottky

diode connected to the OUT pin.

(11) Gate circuit configuration

A resistor is generally inserted between the gate

terminal of the MOSFET and the OUT pin of the IC for

adjustment of switching speed, suppression of voltage

oscillation at the gate terminal and other purposes.

Sometimes, the drive currents for turning-on and -off

must independently determined.

In such a case, connect the gate terminal of the

MOSFET and OUT pin of the IC as shown in Fig.41 or

Fig.42.

In Fig.41, the driving current is limited by Rg1 + Rg2 at

turn-on and by only Rg2 at turn-off

In Fig.42 the driving current is limited by only RG1 at

turn-on and by parallel-connected Rg1 and Rg2 at

turn-off.

Fig. 39

Over Temperature Protection

by Latch Mode for FA5526 / 5527 /5528

Note : OTP Latch by FA5536 / 5537 / 5538 can not

be achieved by above circuit. FA5536 / 5537

/ 5538 may need very complicated circuit for

OTP latch.

Fig.40

Negative voltage prevention circuit

Fig.41

Gate circuit (1)

Fig.42

Gate circuit (2)

FIP4F8S Datasheet(PDF) 30 Page - Fuji Electric

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