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HT46R0664 Datasheet(PDF) 61 Page - Holtek Semiconductor Inc |
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HT46R0664 Datasheet(HTML) 61 Page - Holtek Semiconductor Inc |
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61 / 92 page  Rev. 1.00 60 ����st 1�� �011 Rev. 1.00 61 ����st 1�� �011 HT46R0664 Enhanced A/D+LCD 8-Bit OTP MCU t AD C A/ D c onv er si on ti me 0000B 0010B ST AR T EO CB AC S3 ~A CS 0 Po we r- on Re se t En d of A /D co nv er si on St ar t o f A/ D co nv er si on Re se t A /D co nv er te r A/ D sa mp li ng ti me t A DCS 0000B St ar t o f A/ D co nv er si on Re se t A /D co nv er te r 0001B St ar t o f A /D co nv er si on Re se t A/ D co nv er te r En d of A /D co nv er si on A/ D sa mp li ng ti me t A DCS t AD C A/ D c onv er si on ti me 000000000000B 000000001111B PC R1 1~ PC R0 000000001111B 000000000111B A/ D sa mp li ng ti me t A DCS 000000000000B don' t ca re t AD C A/ D c onv er si on ti me Mi ni mu m one in st ru ct i on cycl e needed, M ax im um t en i ns tr uc ti on c ycl es a ll ow ed En d of A /D co nv er si on A/D Conversion Timing Note: A/D clock must be fSYS/2, fSYS/8 or fSYS/32 tADCS=4tAD tADC=16tAD A/D Conversion Timing After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. Programming Considerations When programming, the special attention must be given to the PCR[11:0] bits in the register. If these bits are all cleared to zero, no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens, the internal A/D circuitry will be power down. Setting the ADONB bit high has the ability to power down the internal A/D circuitry, which may be an important consideration in power sensitive applications. A/D Transfer Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD divided by 4096. The diagram shows the ideal transfer function between the analog input value and the digitised output alue for the A/D converter. Note that to reduce the quantisation error, a 0.5LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5LSB below where they would change without the offset, and the last full scale digitized value will change at a point 1.5LSB below the VDD level. |
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