IO96NDB2V1 datasheet(233/242 Pages) MICROSEMI

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Revision 13

5-1

5 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each version of the ProASIC3L datasheet.

Revision

Changes

Page

Revision 13

(January 2013)

The "ProASIC3L Ordering Information" section has been updated to mention "Y" as

"Blank" mentioning "Device Does Not Include License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43221).

1-III

Added following notes to Table 2-2 • Recommended Operating Conditions 1:

"All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V" (SAR

39910) and "The programming temperature range supported is Tambient = 0°C to 85°C"

(SAR 43645).

2-2

The note in Table 2-212 • ProASIC3L CCC/PLL Specification and Table 2-213 •

ProASIC3L CCC/PLL Specification referring the reader to SmartGen was revised to

refer instead to the online help associated with the core (SAR 42572).

2-132,

2-133

Signal names have been made consistent (SAR 38910).

Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip

(SoC) throughout the document (SAR 40286).

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

Revision 12

(September 2012)

The "Security" section was modified to clarify that Microsemi does not support read-

back of programmed data.

1-2

Revision 11

(August 2012)

Added a Note stating "VMV pins must be connected to the corresponding VCCI pins. See

the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information."

Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating

Conditions 1 (SAR 38316).

2-1

2-2

The "Quiescent Supply Current" section was updated. Table 2-7 • Power Supply State

per Mode is new, and Table 2-9 • Quiescent Supply Current (IDD) Characteristics,

ProASIC3L Sleep Mode* and Table 2-11 • Quiescent Supply Current (IDD)

Characteristics, No Flash*Freeze Mode1 were updated for Core Voltage 1.2 V. Notes

were also updated for Table 2-9, Table 2-10, and Table 2-11 (SAR 34746).

2-7

2-8

The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was changed from

25 mA to 20 mA in the following tables (SAR 37364):

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

Table 2-36 • I/O Output Buffer Maximum Resistances1

Table 2-40 • I/O Short Currents IOSH/IOSL

Table 2-134 • Minimum and Maximum DC Input and Output Levels

Table 2-138 • Minimum and Maximum DC Input and Output Levels

Also added note stating "Output drive strength is below JEDEC specification." for Tables

Table 2-29, Table 2-32, Table 2-36, and Table 2-40.

Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected

from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in table Table 2-23

(SAR 39715).

2-22

2-27

2-30

2-34

2-38

2-83

2-85

IO96NDB2V1 Datasheet(PDF) 233 Page - Microsemi Corporation

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