IO96NDB2V1 datasheet(235/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

5-3

Revision 10

continued

3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to applicable tables in the

"Overview of I/O Performance" section and "Detailed I/O DC Characteristics" section.

Values for 1.2 V LVCMOS were added to tables in the "Detailed I/O DC Characteristics"

section. The "3.3 V LVCMOS Wide Range" section and "1.2 V LVCMOS Wide Range"

section, with Minimum and Maximum DC Input and Output Levels tables, are new.

Complete timing data for wide range will be available in a later revision of the datasheet

(SARs 37161, 38188).

2-22,

2-33,

2-50,

2-80

The notes regarding drive strength in the "Summary of I/O Timing Characteristics –

Default I/O Software Settings" section tables were revised for clarification. They now

state that the minimum drive strength for the default software configuration when run in

wide range is ±100 µA. The drive strength displayed in software is supported in normal

range only. For a detailed I/V curve, refer to the IBIS models (SAR 34761).

2-26

Table 2-39 • I/O Weak Pull-Up/Pull-Down Resistances was updated with additional

values and the definitions of RWEAK PULL-UP-MAX and RWEAK PULL-DOWN-MAX were

corrected (SAR 34756).

2-37

The paragraph above Table 2-44 • Duration of Short Circuit Event before Failure was

revised to change the maximum temperature from 110°C to 100°C, with an example of

six months instead of three months. The row for 110°C was removed from the table for

consistency with Table 2-2 • Recommended Operating Conditions 1 (SAR 34744).

2-41

The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated

to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software

Settings" section (SAR 34890).

2-42,

2-26

The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34797): "It

uses a 5 V–tolerant input buffer and push-pull output buffer."

2-52

The table notes were revised for LVDS Table 2-174 • Minimum and Maximum DC Input

and Output Levels (SAR 34813).

2-100

Values for the maximum frequency for input and output DDR were added to tables in the

"DDR Module Specifications" section (SAR 34805).

2-115

Minimum pulse width High and Low values were added to the tables in the "Global Tree

Timing Characteristics" section. The maximum frequency for global clock parameter

was removed from these tables because a frequency on the global is only an indication

of what the global network can do. There are other limiters such as the SRAM, I/Os, and

PLL. SmartTime software should be used to determine the design frequency (SAR

36965).

2-128

Table 2-212 • ProASIC3L CCC/PLL Specification and Table 2-212 • ProASIC3L

CCC/PLL Specification were updated. A note was added to indicate that when the

CCC/PLL core is generated by Microsemi core generator software, not all delay values

of the specified delay increments are available (SAR 34825).

2-132,

2-133

Figure 2-46 • Write Access after Write onto Same Address, Figure 2-47 • Read Access

after Write onto Same Address, and Figure 2-48 • Write Access after Read onto Same

Address were deleted. Reference was made to a new application note, Simultaneous

Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which

covers these cases in detail (SAR 34873).

The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"

tables, Figure 2-50 • FIFO Reset, and the FIFO "Timing Characteristics" tables were

revised to ensure consistency with the software names (SAR 35751).

2-135,

2-138,

2-144,

2-146

Figure 2-48 • FIFO Read and Figure 2-49 • FIFO Write are new (SAR 34849).

2-143

The "Pin Descriptions and Packaging" chapter is new (SAR 34773).

3-1

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