IO96NDB2V1 datasheet(234/242 Pages) MICROSEMI

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Datasheet Information

5-2

Revision 13

Revision 11

continued

Figure 2-12 • AC Loading in the "3.3 V PCI, 3.3 V PCI-X" section was updated to match

Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads (SAR 34890).

2-81

In Table 2-180 • Minimum and Maximum DC Input and Output Levels, VIL and VIH were

revised so that the maximum is 3.6 V for all listed values of VCCI (SAR 37690).

2-103

The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"

section in the "Pin Descriptions and Packaging" chapter: "Within the package, the VMV

plane is decoupled from the simultaneous switching noise originating from the output

buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the

input stage of the I/Os in the I/O banks” (SAR 38316). The datasheet mentions that

"VMV pins must be connected to the corresponding VCCI pins" for an ESD

enhancement.

3-1

Pin K15 of the "FG484" pin table for A3P600L was corrected from VvB1 to VCCIB1

(SAR 38788).

4-35

Revision 10

(May 2012)

The "In-System Programming (ISP) and Security" section and "Security" section were

revised to clarify that although no existing security measures can give an absolute

guarantee, Microsemi FPGAs implement the best security available in the industry

(SAR 34670).

1-2

The Y security option and Licensed DPA Logo were added to the "ProASIC3L Ordering

Information" section. The trademarked Licensed DPA Logo identifies that a product is

covered by a DPA counter-measures license from Cryptography Research (SAR

34728).

III

The "ProASIC3L Device Status" table was updated to show that all ProASIC3L devices

have changed in status from Advance to Production (SAR 38198).

The opening sentence of the "General Description" section was revised for clarity to

"The ProASIC3L family of Microsemi flash FPGAs dramatically reduces dynamic power

consumption by 40% and static power by 50% compared to the equivalent ProASIC3

device" (SAR 22661).

1-1

The following sentence was removed from the "Advanced Architecture" section:

"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage

(3.3 V) programming of ProASIC3L devices via an IEEE 1532 JTAG interface" (SAR

34690).

1-3

The "Specifying I/O States During Programming" section is new (SAR 34700).

1-8

Table 1-1 • I/O Standards Supported is new. The "I/Os with Advanced I/O Standards"

section was revised to add definitions of hot-swap and cold-sparing (SAR 37732).

1-7

In Table 2-2 • Recommended Operating Conditions 1, VPUMP programming voltage for

operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR 32257).

2-2

Values for 1.5 V were added to Table 2-8 • Quiescent Supply Current (IDD)

Characteristics, ProASIC3L Flash*Freeze Mode* and Table 2-11 • Quiescent Supply

Current (IDD) Characteristics, No Flash*Freeze Mode1 (SAR 30578).

2-7,

2-8

The reference to guidelines for global spines and VersaTile rows, given in the "Global

Clock Contribution—PCLOCK" section, was corrected to t

he "Spine Architecture"

section of the Global Resources chapter in the ProASIC3L FPGA Fabric User's

Guide (SAR 34737).

2-15

tDOUT was corrected to tDIN in Figure 2-4 • Input Buffer Timing Model and Delays

(example) (SAR 37110).

2-19

Revision

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