IO96NDB2V1 datasheet(237/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

5-5

Revision

Changes

Page

Revision 9 (Feb 2009)

Product Brief v1.3

The "I/Os Per Package 1" table was revised to change the number of differential

I/O pairs for A3PE3000L from 300 to 310.

Table 2 • ProASIC3L FPGAs Package Sizes Dimensions is new.

Revision 8 (Feb 2009)

Product Brief v1.2

The "Advanced and Pro (Professional) I/Os" section was revised to add two

bullets regarding wide range power supply voltage support.

3.0 V wide range was added to the list of supported voltages in the "I/Os with

Advanced I/O Standards" section. The "Wide Range I/O Support" section is new.

1-7

Revision 7 (Aug 2008)

and

Switching

Characteristics

Advance v0.6

3.0 V LVCMOS wide range support data was added to Table 2-2 • Recommended

Operating Conditions 1.

2-2

3.3 V LVCMOS wide range support data was added to Table 2-23 • Summary of

Maximum and Minimum DC Input and Output Levels Applicable to Commercial

and Industrial Conditions—Software Default Settings to Table 2-25 • Summary of

Maximum and Minimum DC Input and Output Levels Applicable to Commercial

and Industrial Conditions—Software Default Settings.

2-22 to

2-24

3.3 V LVCMOS wide range support data was added to Table 2-27 • Summary of

AC Measuring Points.

2-26

3.3 V LVCMOS wide range support text was added to the "3.3 V LVTTL / 3.3 V

LVCMOS" section.

2-42

Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS

3.3 V Wide Range is new.

2-50

Revision 6 (Aug 2008)

DC and Switching

Characteristics

Advance v0.5

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was

updated to add several new rows of values.

2-7

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L

Flash*Freeze Mode* through Table 2-11 • Quiescent Supply Current (IDD)

Characteristics, No Flash*Freeze Mode1 were updated to add 1.5 V core voltage.

2-7 to 2-8

Table 2-19 • Different Components Contributing to Dynamic Power Consumption

in ProASIC3L Devices at 1.5 V VCC is new.

2-14

Table 2-20 • Different Components Contributing to the Static Power Consumption

in ProASIC3L Devices was updated to add the static PLL contribution at 1.5 V

core operation.

2-14

Timing tables were updated to include tables for 1.5 V core voltage.

N/A

Table 2-212 • ProASIC3L CCC/PLL Specification was updated for core voltage

1.2 V and Table 2-213 • ProASIC3L CCC/PLL Specification for 1.5 V is new.

2-132,

2-133

Revision 5 (Jul 2008)

Product Brief v1.1

DC and Switching

Characteristics

Advance v0.4

As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core

voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to

1.5 V.

N/A

IO96NDB2V1 Datasheet(PDF) 237 Page - Microsemi Corporation

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