Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

CS42L50 Datasheet(PDF) 12 Page - Cirrus Logic

Part # CS42L50
Description  Low Voltage, Stereo CODEC with headphone Amp
PDF  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42L50 Datasheet(HTML) 12 Page - Cirrus Logic

Back Button CS42L50 Datasheet HTML 8Page - Cirrus Logic CS42L50 Datasheet HTML 9Page - Cirrus Logic CS42L50 Datasheet HTML 10Page - Cirrus Logic CS42L50 Datasheet HTML 11Page - Cirrus Logic CS42L50 Datasheet HTML 12Page - Cirrus Logic CS42L50 Datasheet HTML 13Page - Cirrus Logic CS42L50 Datasheet HTML 14Page - Cirrus Logic CS42L50 Datasheet HTML 15Page - Cirrus Logic CS42L50 Datasheet HTML 16Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 48 page
background image
CS42L50
12
DS544PP1
SWITCHING CHARACTERISTICS (T
A = -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
16.
There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
Parameters
Symbol
Min
Typ
Max
Units
Input Sample Rate
Single Speed Mode
Double Speed Mode
Fs
Fs
2
50
-
-
50
100
kHz
kHz
MCLK Pulse Width High
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
35
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
35
-
-
ns
Master Mode
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDOUT Valid
tsdo
0
-
20
ns
SCLK Duty Cycle
40
50
60
%
Slave Mode
LRCK Duty Cycle
40
50
60
%
Rise Time of Both LRCK and SCLK
tr
-
-
10
ns
Fall Time of Both LRCK and SCLK
tf
-
-
10
ns
SCLK Period (Note 16)
Single Speed Mode
Double Speed Mode
tsclkw
tsclkw
-
-
-
-
ns
ns
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDOUT Valid
Single Speed Mode
Double Speed Mode
tdss
tdss
-
-
-
-
ns
ns
1
128
()Fs
----------------------
1
64
()Fs
------------------
1
(512)Fs
1
(256)Fs



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com