CS42L50 datasheet(34/48 Pages) CIRRUS

34 / 48 page

CS42L50

DS544PP1

no operation is required. Please note that the inter-

nal registers are separated into two unique chip ad-

dress blocks, one for the control of the ADC and

one for the control of the DAC portion of the codec.

SDA is a bidirectional data line. Data is clocked

into and out of the part by the clock, SCL, with the

clock to data relationship as shown in Figure 5.

The upper 6 bits of the 7 bit address field must be

001000. To communicate with the CS42L50, the

chip address should match that of the ADC

(0010000) or DAC (0010001) address. The eighth

bit of the address byte is the R/W bit (high for a

read, low for a write). If the operation is a write, the

next byte is the Memory Address Pointer, MAP,

which selects the register to be read or written. The

MAP is then followed by the data to be written. If

the operation is a read, the contents of the register

pointed to by the MAP will be output after the chip

address.

The CS42L50 has MAP auto increment capability,

enabled by the INCR bit in the MAP register. If

INCR is 0, then the MAP will stay constant for suc-

cessive writes. If INCR is set to 1, then MAP will

auto increment after each byte is written, allowing

block reads or writes of successive registers.

CS42L50 Datasheet(PDF) 34 Page - Cirrus Logic