CS42L50 datasheet(19/48 Pages) CIRRUS

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CS42L50

DS544PP1

4.1.6 Interface Control (address 02h)

4.1.7

MASTER CLOCK DIVIDE (MCLKDIV)

Default = 0

0 - Disabled

1 - Enabled

Function:

Divides ADC MCLK by two prior to all other chip circuitry.

4.1.8

MASTER CLOCK RATIO (RATIO)

Default = 00

00 - 128x

01 - 192x

10 - 256x

11 - 384x

Function:

Sets the ratio of MCLK to LRCK for the ADC.

4.1.9

MASTER MODE (MASTER)

Default = 0

0 - Slave Mode

1 - Master Mode

Function:

Configures the CS42L50 for master or slave operation.

4.1.10 DIGITAL INTERFACE FORMAT (DIF)

Default = 000

000 - I2S, up to 24-bit data, data valid on positive edge of SCLK

001 - Left Justified, up to 24-bit data, data valid on positive edge of SCLK

010 - Reserved

011 - Right Justified, 16-bit data, data valid on positive edge of SCLK

100 - Right Justifed, 24-bit data, data valid on positive edge of SCLK

101 - Right Justified, 18-bit data, data valid on positive edge of SCLK

110 - Right Justified, 20-bit data, data valid on positive edge of SCLK

111 - Reserved

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital

Interface Format and the options are detailed in Figures 25 through 30. It is recommended that the ADC

and the DAC are configured for the same Digital Interface Format.

765

4321

RESERVED

MCLKDIV

RATIO1

RATIO0

MASTER

DIF2

DIF1

DIF0

000

0000

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