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LM4935RLEVAL Datasheet(PDF) 16 Page - Texas Instruments |
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LM4935RLEVAL Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 91 page  SDA SCL 1 8 2 3 7 6 5 8 10 4 9 1 7 ack from slave ack from slave w rs r stop ack from slave ack from master repeated start data from slave start w ack ack rs r ack ack stop start SCL SDA MSB Chip Address LSB slave address = 00110102 register address = 0x00h MSB Register 0x00h LSB MSB Data LSB MSB Chip Address LSB slave address = 00110102 register 0x00h data ack ack ack ack start MSB Chip Address LSB w ack MSB Register 0x02h LSB ack MSB Data LSB ack stop ack from slave ack from slave ack from slave SCL SDA start slave address = 00110102 w ack register address = 0x02h ack ack register 0x02h data stop ADR6 Bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 MSB LSB I 2 C SLAVE address (chip address) LM4935, LM4935RLEVAL SNAS296D – OCTOBER 2005 – REVISED MARCH 2006 www.ti.com Figure 4-2. I2C Chip Address Register changes take an effect at the SCL rising edge during the last ACK from slave. w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Figure 4-3. Example I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. Figure 4-4. Example I2C Read Cycle Figure 4-5. I2C Timing Diagram 4.1.5 I 2C TIMING PARAMETERS Symbol Parameter Limit Units Min Max 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 16 Application Information Copyright © 2005–2006, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL |
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