LM4935RLEVAL datasheet(19/91 Pages) TI1

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LM4935, LM4935RLEVAL

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SNAS296D – OCTOBER 2005 – REVISED MARCH 2006

Table 4-1. Register Map (continued)

Address

0x24h

TRIG_2

TRIG_2 [3:0]

SOURCE

DIR

ENB

0x25h

TRIG_2_M

TRIG_2 [11:4]

0x26h

DEBUG

GPIO_TES

RSVD

SOFT

RSVD

RESET

_MODE

For all registers, the default setting of data bits 7 through 0 are all set to zero.

RESERVED bits should always be set to zero.

4.2.1

BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip.

Table 4-2. BASIC (0x00h)

Bits

Field

Description

1:0

CHIP_MODE

The LM4935 can be placed in one of four modes which dictate its basic operation. When a new mode is

selected the LM4935 will change operation silently and will re-configure the power management profile

automatically. The modes are described as follows:

CHIP MODE

Audio System

Detection System

Typical Application

002

Off

Power-down Mode

012

Off

Stand-by mode with headset event detection

102

Off

Active without headset event detection

112

Active with headset event detection

PLL_ENABLE

If set the PLL can be used.

USE_OSC

If set the power management and control circuits will assume that no external clock is available and will resort

to using an on-chip oscillator for SAR, headset detection and analog power management functions such as

click and pop.

5:4

CAP_SIZE

Programs the extra delays required to stabilize once charge/discharge is complete, based on the size of the

bypass capacitor.

CAP_SIZE

Bypass Capacitor Size

Turn-off/on time

002

0.1 µF

45 ms/75 ms

012

1 µF

45 ms/140 ms

102

2.2 µF

45 ms/260 ms

112

4.7 µF

45 ms/500 ms

STEREO

If set, the mixers assume that the signals on the left and right internal busses are highly correlated and when

these signals are combined their levels are reduced by 6 dB to allow enough headroom for them to be summed

at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the Headphone amplifier, if this bit is set,

the left and right signal levels are routed to the corresponding left or right headphone output; if this bit is

cleared, the left and the right signals are added and routed to both headphone outputs and their levels are

reduced by 6dB to allow enough headroom.

OCL

If set the part is placed in OCL (Output Capacitor Less) mode.

For reliable headset / push button detection the following bits should be defined before enabling the

headset detection system by setting bit 0 of CHIP_MODE:

The OCL-bit (Cap / Capless headphone interface; bit 7 of this register)

The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))

The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))

The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))

All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and

should not be altered while the audio sub-system is active.

Application Information

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