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LM4935RLEVAL Datasheet(PDF) 45 Page - Texas Instruments |
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LM4935RLEVAL Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 91 page  LM4935, LM4935RLEVAL www.ti.com SNAS296D – OCTOBER 2005 – REVISED MARCH 2006 4.2.41 SAR TRIGGER 2 CONFIGURATION REGISTER This register is used to setup a voltage trigger on one of the SAR outputs. Table 4-42. TRIG_2 (0x24h) Bits Field Description 0 TRIG_2_ENB Enables the 2nd SAR trigger interrupt, if cleared will clear the IRQ. 1 TRIG_2_DIR Selects the direction the voltage should be moving: TRIG_2_DIR Trigger if signal passes: 0 Above Threshold 1 Below Threshold 3:2 TRIG_2_SOURCE Programs the channel used by the trigger TRIG_2_SOURCE Source 002 VSAR_1 012 VSAR_2 102 D_VDD/2 or BB_VDD 112 A_VDD/2 7:4 TRIG_2_LSB Sets bits 3:0 of the threshold used by the trigger. 4.2.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER This register is used to setup the threshold of a voltage trigger on one of the SAR outputs. Table 4-43. TRIG_2_MSB (0x25h) Bits Field Description 7:0 TRIG_2_MSB Sets bits 11:4 of the threshold used by the trigger. 4.2.43 DEBUG REGISTER This register is used to set test modes within the device. Table 4-44. DEBUG (0x26h) Bits Field Description 0 RSVD Reserved 1 RSVD Reserved 2 RSVD Reserved 3 SOFT_RESET This field can be used to reset the chip without a power cycle. 4 RSVD Reserved 5 RSVD Reserved 6 RSVD Reserved 7 GPIO_TEST_MODE If set and GPIO_SEL = '010', then the GPIOs are configured to interface with the LMV1026 digital microphone as long as AUDIO_IF_MODE (0x19h) is not set to '11'. GPIO_SEL GPIO 1 GPIO 2 0002 RSVD RSVD 0012 RSVD RSVD 0102 VADC_CLOCK_OUT DIG_MIC_IN 0112 RSVD RSVD 1002 RSVD RSVD 1012 RSVD RSVD 1102 RSVD RSVD 1112 RSVD RSVD Copyright © 2005–2006, Texas Instruments Incorporated Application Information 45 Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL |
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