LM4935RLEVAL datasheet(17/91 Pages) TI1

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CLK

SDI

TSPISETENB

TSPIHOLDD

TSPISETD

TSPICH

TSPIT

TSPICL

TSPIHOLDENB

TEST_MODE/CS

SDI

CLK

Ignored

Address

SAR Data

GPIO2

TEST_MODE/CS

SDI

CLK

Write Data

TEST_MODE/CS

LM4935, LM4935RLEVAL

www.ti.com

SNAS296D – OCTOBER 2005 – REVISED MARCH 2006

Data Hold Time (Output direction, delay generated by LM4935)

300

900

Data Hold Time (Input direction, delay generated by the Master)

900

Data Setup Time

100

Rise Time of SDA and SCL

20+0.1Cb

300

Fall Time of SDA and SCL

15+0.1Cb

300

Set-up Time for STOP condition

600

Bus Free Time between a STOP and a START Condition

1.3

µs

Capacitive Load for Each Bus Line

200

Method 2. SPI/Microwire Control/3–wire Control

The LM4935 can be controlled via a three wire interface consisting of a clock, data and an active low

chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the

chip_select as follows:

Figure 4-6. SPI Write Transaction

If the application requires read access to the register set; for example to determine the cause of an

interrupt request or to read back a SAR data field, the GPIO2 pin can be configured as an SPI format

serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to SPI_SDO. To

perform a read rather than a write to a particular address the MSB of the register address field is set to a

1, this effectively mirrors the contents of the register field to read-only locations above 0x80h:

Figure 4-7. SPI Read Transaction

Figure 4-8. SPI Timing - Three Wire Mode Write Bus Timing

Application Information

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LM4935RLEVAL Datasheet(PDF) 17 Page - Texas Instruments

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