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GMS81032 Datasheet(PDF) 42 Page - Hynix Semiconductor |
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GMS81032 Datasheet(HTML) 42 Page - Hynix Semiconductor |
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42 / 101 page  4 - 4 - - WDTON ENPCK BTCL BTS2 BTS1 BTS0 CKCTLR W <00C7H> ENPCK 0 1 Peripheral Clock Stopped Provided 7 0 Clock Control Register 4.1.4 Basic Interval Timer (B.I.T) - 8bit binary counter - Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on - Secures the oscillation stabilization time in standby mode (stop mode) release - Contents of B.I.T can be read - Provides the clock for watch dog timer. - - WTON ENPCK BTCL BTS2 BTS1 BTS0 MUX BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 CKCTLR BITR IFBIT PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 DATA BUS Fig. 4.4 Block diagram of Basic Interval Timer Chapter 4. Peripheral Hardware DATA BUS |
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