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GMS81032 Datasheet(PDF) 72 Page - Hynix Semiconductor |
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GMS81032 Datasheet(HTML) 72 Page - Hynix Semiconductor |
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72 / 101 page ![]() 5 - 7 Clock SYNC R/W INTERNAL ADDR. BUS INTERNAL DATA BUS INTERNAL READ INTERNAL WRITE PC SP SP-1 SP-2 LVA*2 HVA*3 NEW PC OP CODE OP CODE PCH PCL PSW ¡ÈL¡È VECTOR ¡ÈH¡È VECTOR Fig. 5. 3 Interrupt Procesing Step Timing *1 ISR : Interrupt Service Routine *2 LVA : Low Vector Address *3 HVA : High Vector Address 5.1 SOFTWARE INTERRUPT 5.5.1 Interrupt by Break(BRK) Instruction Software interrupt is available just by writing ¡ÈBreak(BRK)¡È instruction. The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set and I flag is reset. N V G B H I Z C Flag change by BRK execution PSW N V G 1 H 0 Z C PSW set reset (Right after BRK execution) Chapter 5. Interrupt Interrupt Process Step ISR*1 |
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