GMS81032 datasheet(59/101 Pages) HYNIX

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4.2.3 Timer0, Timer1

TIMER0 and TIMER1 have an up-counter. When value of the up-counter

reaches the content of Timer Data Register(TDR), the up-counter is cleared to

¡È00H¡È, and interrupt(IFT0, IFT1) is occured at the next clock

Fig. 4. 10 Operatiion of Timer0

Concurrence

CLEAR

T0 Data

Registers

Value

T0 Value

INTERRUPT

Interval period

IFT0

For Timer0, the internal clock(PS) and the external clock(EC) can be selected as

counter clock. But Timer1 and Timer2 use only internal clock. As internal clock.

Timer0 can be used as internal-timer which period is determined by Timer Data

The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST,

CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are

used to stop and start Timer0 and Timer1 without clearing the counter. T0ST,

T1ST is used to clear the counter. For clearing and starting the counter, T0ST

or T1ST should be temporarily set to ¡È0¡È and then set to ¡È1¡È. T0CN,

T1CN, T0ST and T1ST should be set ¡È1¡È, when Timer counting-up.

Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0

to ¡È1¡È, the period of signal from INT2 can be measured and then, event

counter value for INT2 can be read.

Chapter 4. Peripheral Hardware

GMS81032 Datasheet(PDF) 59 Page - Hynix Semiconductor