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GMS81032 Datasheet(PDF) 69 Page - Hynix Semiconductor |
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GMS81032 Datasheet(HTML) 69 Page - Hynix Semiconductor |
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69 / 101 page  5 - 4 5.3 INTERRUPT ACCEPT MODE The interrupt priority order is determined by bit(IM1, IM0) of IMOD register. - - IM1 IM0 IP3 IP2 IP1 IP0 IMOD R/W <00CAH> 7 0 Interrupt Mode Register IM1 IM0 Priority 0 0 Fixed by H/W 0 1 Changeable by IP 3-0 1 * Interrupt is inhibited 5.3.1 Selection of interrupt by IP3 - IP0 The condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be ¡È1¡È. IP3 0 0 0 0 0 0 0 1 1 1 1 1 IP2 0 0 0 1 1 1 1 0 0 0 0 1 IP1 0 1 1 0 0 1 1 0 0 1 1 0 IP0 1 0 1 0 1 0 1 0 1 0 1 0 Selection interrupt KSCNR (Key Scan) INT1R (External interrupt 1) INT2R (External interrupt 2) Reserved T0R (Timer 0) T1R (Timer 1) T2R (Timer 2) Reserved Reserved WDTR (Watch Dog Timer) BITR (Basic Interval Timer) Reserved Table 5.2 Interrupt Selection by IP3 - IP0 Chapter 5. Interrupt Assigning by interrupt accept mode bit *In Reset state, these IP3 - IP0 registers become all ¡È0¡È. |
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