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82375EB Datasheet(PDF) 19 Page - Intel Corporation

Part # 82375EB
Description  PCI-EISA BRIDGE (PCEB)
PDF  131 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82375EB Datasheet(HTML) 19 Page - Intel Corporation

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82375EBSB
Pin Name
Type
Description
MEMACK
in
MEMORY ACKNOWLEDGE
MEMACK
is the response handshake that indicates
to the PCEB that the function requested over the MEMREQ
andor FLSHREQ
signals has been completed
If the PCEB is configured for Guaranteed Access Time Mode through the Arbiter
Control Register and both MEMREQ
and FLSHREQ
are asserted the assertion
of MEMACK
indicates to the PCEB that ownership of main memory has been
granted and that all system buffers have been flushed and temporarily disabled
If MEMACK
is asserted in response to assertion of MEMREQ
(GAT either
enabled or disabled) it indicates that the system’s buffers pointing towards the main
memory are flushed and temporarily disabled so that APIC can proceed with the
interrupt message sequence
If FLSHREQ
is asserted and MEMREQ
is not asserted (with GAT mode being
either enabled or disabled) the assertion of MEMACK
indicates that the system’s
posted write buffers pointing towards PCI are flushed and temporarily disabled and
the EISA Bus can be granted to an EISA master or DMA
This signal is synchronous to the PCI clock
23 Address Decoder Signals
Pin Name
Type
Description
MEMCS
out
MEMORY CHIP SELECT
MEMCS
is a programmable address decode signal
provided to a Host CPU bridge A Host bridge can use MEMCS
to forward a PCI cycle
to the main memory behind the bridge MEMCS
is asserted one PCI clock after
FRAME
is sampled asserted (address phase) and is valid for one clock cycle before
being negated MEMCS
is driven high during reset
PIODEC
in
PCI IO SPACE DECODER
PIODEC
can be used to provide arbitrarily complex
EISA-to-PCI IO address space mapping This signal can be connected to the decode
select output of an external IO address decoder When PIODEC
is asserted during
an EISA IO cycle that cycle is forwarded to the PCI Bus
Note that an external pull-up resistor is required if this input signal is not used (ie not
driven by the external logic)
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