82375EB datasheet(72/131 Pages) INTEL

72 / 131 page

82375EBSB

515 BASIC WRITE

Figure 9 shows the PCEB as a master writing to PCI memory in zero wait states Figure 10 shows the fastest

response of the PCEB as a target to a memory or IO write transaction generated by a PCI master

As a PCI master

the PCEB performs memory write and IO transfers If buffering of memory accesses is

enabled write transfers are posted When writing data to PCI memory the PCEB writes a maximum of 16

bytes (one line of the Line Buffer) using a burst write cycle IO writes are always non-buffered transactions

The PCEB generates PCI write cycles on behalf of EISA masters and DMA devices and when the PCEB

flushes its internal Line Buffer

As a PCI target

the PCEB responds to both IO and memory write transfers If the EISA Bus is occupied the

PCI write is retried by the PCEB When the PCEB owns the EISA Bus the transaction proceeds For burst IO

writes the PCEB always target terminates after the first data transaction by asserting STOP

and TRDY

the end of the first data phase During a burst memory write the PCEB always target terminates after the first

data phase

Figure 10 shows the fastest PCEB response to a write cycle targeted to an internal PCI configuration register

During IO or memory write accesses to the EISA Bus the PCEB always adds wait states The PCEB adds

wait states by holding TRDY

high until the transfer on the EISA Bus is completed

290477 – 51

Figure 9 PCEB Write to PCI Memory

82375EB Datasheet(PDF) 72 Page - Intel Corporation