PM0020 datasheet(80/87 Pages) STMICROELECTRONICS

80 / 87 page

ISC logic description

PM00020

80/87

Security status is not activated until the device exits from ISC mode (ISC_DISABLE

instruction is executed or a Test-Logic-Reset is issued). For example, after

ISC_PROGRAM_SECURITY is executed, array verification is still allowed until exiting of

ISC mode, but, however, the only way to erase the Security bit is a full chip erase, even

before exiting ISC mode.

If the Security bit is set and a full chip erase is executed, the device will be unblocked only

after it exits from ISC mode.

When the Security bit is programmed the signal ISC_DEBUG_EN becomes low at once,

without expecting to exit from ISC mode, in the same way, when a full chip erase is

executed, the ISC_DEBUG_EN becomes high at once.

Table 46.

ISC_PROGRAM_SECURITY sequence

Step

Tap activity

Comment

Run-Test/Idle

Start

IR-Scan

Load ISC_ADDRESS_SHIFT

DR-Scan

Shift in 8 bits security dummy

address, 80 Hex

3IR-Scan

Load

ISC_PROGRAM_SECURITY

Run-Test/Idle

Security bit program begins

DR-Scan

Shift out status

Begin polling

IR-Scan

Load ISC-NOOP

DR-Scan

Shift out status

Repeat step 7until ready = 1

Run-Test/Idle

End

PM0020 Datasheet(PDF) 80 Page - STMicroelectronics