PM0020 datasheet(38/87 Pages) STMICROELECTRONICS

38 / 87 page

STR91xFA Flash memory

PM00020

38/87

1.15.6

FMI status register (FMI_SR)

Address Offset: 5400 001Ch

Reset value: 0000 0000h

Bit 5

Reserved, always read as 0

Bit 4

NBBEN: Flash Non Boot Bank enable

This bit is set and cleared by software. It enables/disables Flash Non Boot bank.

0: Disabled

1: Enabled.

Bit 3

BBEN: Flash Boot Bank enable

This bit is set and cleared by software. It enables/disables Flash Boot bank.

0: Disabled

1: Enabled

Bits 2:0

Reserved, always read as 0

Reserved

PFQ

BCEN

Res.

B1ERR

B0ERR

rc_w1

Bits 31:5

Reserved, always read as 0

Bit 4

PFQBCEN: PFQBCEN Status

This bit is set and cleared by harware.

0: PFQ/BC disabled (bypassed)

1: PFQ/BC enabled

Bit 3

OM: Out of Memory error

This bit is set by hardware and cleared by software writing 1. It indicates that an

access was made outside the configured memory area. An interrupt is generated if

the OMIE bit in the FMI_CR regsiter is set.

0: No OM error

1: An Out of Memory error occurred

Bit 2

Reserved, always read as 0

Bit 1

B1ERR: Flash Bank 1 error

This bit is set by hardware and cleared by software writing 1. It indicates that an

access was made to Bank 1 while it was disabled. An interrupt is generated if the

BERRIE bit in the FMI_CR register is set.

0: No B1ERR error

1: A Flash Bank 1 error occurred

Bit 0

B0ERR: Flash Bank 0 error

This bit is set by hardware and cleared by software writing 1. It indicates that an

access was made to Bank 0 while it was disabled. An interrupt is generated if the

BERRIE bit in the FMI_CR register is set.

0: No B0ERR error

1: A Flash Bank 0 error occurred

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