PM0020 datasheet(16/87 Pages) STMICROELECTRONICS

16 / 87 page

STR91xFA Flash memory

PM00020

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1.4

Boot configuration

In the default configuration, after reset the first sector of Bank 0 is enabled and resides at

0x0000.0000h so that the device boots from Bank 0, and Bank 1 is disabled.

Using the JTAG interface, you can configure the device to boot from Bank 1. The selection of

which Flash memory is at the boot location is programmed in a non-volatile Flash-based

configuration bit. The firmware cannot change this configuration bit, only the JTAG interface

has access.

1.5

Electronic signature

The electronic signature can be read via JTAG or from the application using the RSIG

command (Section 1.11.2).

The ISC IDCODE assigned to the Flash memory die is 04570041h.

Note:

The electronic signature read by the RSIG command contains the JTAG ID code of the

Flash memory die. To get the STR91xFA product ID and revision level, read the last two

bytes of the OTP sector.

1.6

OTP sector

The device provides 240 bits of user OTP memory. The last 16 bits in the 256-bit sector are

reserved for the STR91xFA product ID and revision level and programmed by ST. You can

read all these bits, and program any unprogrammed bits via JTAG or from the application

using the ROTP and WOTP commands (see Section 1.11.3 and Section 1.12.8 . The OTP

sector can be locked via JTAG or CUI command to prevent any modification. The OTP lock

status bit is stored in the Protection Level 2 register which can be read by the application.

Refer to Section 1.13.2).

1.7

Power down mode

In STR91xFA low power modes, the Flash automatically reduces its power consumption and

can be read immediately after wake-up.

When the STR91xFA is in low power mode, you can put the Flash in Power Down mode as

well for lower power consumption. You do this by programming the PWD bit in the Flash

Configuration register (see Section 1.13.6). The consumption is drastically reduced, but

after wake-up from low power, a delay is inserted automatically to ensure the Flash is

operational before the CPU starts execution.

1.8

JTAG interface

The device can be erased and programmed by sending commands to the command

interface described in Table .

The device can also be programmed through the 4 pin JTAG port which is 1532 standard

compliant and supports standard ISC (In System Configuration) programming instructions.

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