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AN4617 Datasheet(PDF) 7 Page - STMicroelectronics |
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AN4617 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 26 page  DocID027161 Rev 1 7/26 AN4617 Peripheral migration 25 Table 4. STM32 peripheral compatibility analysis F0 versus L0 series Peripheral F0 series L0 series Compatibility Possible differences from user point of view Pinout FW driver compatibility SPI Yes++ Yes FIFO availability Data size selection Data packing Identical Partial WWDG Yes Yes+ None NA Full IWDG Yes Yes+ None NA Full DBGMCU Yes Yes+ Sleep mode control Identical for the SWD Partial CRC Yes Yes None NA Full NVIC Yes Yes+ EXTI vectors Wake up capability Internal event sources Identical for the same feature Partial DMA Yes Yes+ Remapping control NA Partial TIM Yes Yes+ Number of timers Functionality Low power timer Identical for the same feature Partial PWR Yes Yes+ Dynamic voltage scaling BOR threshold control Low power modes Fast wake up Internal reset sources Identical for the same feature Partial RCC Yes Yes+ Internal clock sources CSS on LSE Internal clock measurement Calibration capability Identical for the same feature except OSC32 for small packages Partial USART Yes Yes+ Low power UART Identical for the same feature Partial I2C Yes Yes+ None Identical Full DAC Yes Yes+ Supply range HW trigger Identical for the same feature Partial ADC Yes Yes++ Supply range HW trigger HW oversampling Low frequency mode Interrupt sources Identical for the same feature Partial COMP Yes Yes+ Ultra low power Speed, hysteresis Outputs/Inputs Identical for the same feature Partial RTC Yes Yes+ Number of alarms Triggers from tamper events Identical for the same feature Partial FLASH Yes Yes+ Sector & firewall protection NA Partial RAM Yes Yes Firewall protection (L0 only) Parity check (F0 only) NA Partial |
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