DocID027161 Rev 1

11/26

AN4617

Peripheral migration

25

Note:

NA = Not applicable - Feature not available

Note:

F0 devices have only one APB bus, APB1 and APB2 used in L0 devices indicate on which

APB register the clock configuration bits of those peripherals are defined.

Note:

Recent products can feature additional peripherals (such as expanded GPIO ports, GP

timers and other digital or analog ones). User has to refer to the latest available

documentation.

LPTIM1

APB

NA

APB1

0x40007C00

CEC

0x40007800

NA

I2C3

NA

0x40007800

DAC / DAC1

0x40007400

0x40007400

PWR

0x40007000

0x40007000

CRS

0x40006C00

0x40006C00

CAN

0x40006400

NA

USB/CAN SRAM

0x40006000

0x40006000

USB / USB FS

0x40005C00

0x40005C00

I2C2

0x40005800

0x40005800

I2C1

0x40005400

0x40005400

USART5

0x40005000

0x40005000

USART4

0x40004C00

0x40004C00

USART3 / LPUART1

0x40004800

0x40004800

USART2

0x40004400

0x40004400

SPI2

0x40003800

0x40003800

IWDG

0x40003000

0x40003000

WWDG

0x40002C00

0x40002C00

RTC + BKP_REG

0x40002800

0x40002800

LCD

NA

0x40002400

TIM14

0x40002000

NA

TIM7

0x40001400

0x40000C00

TIM6

0x40001000

0x40001000

TIM3

0x40000400

0x40000400

TIM2

0x40000000

0x40000000

Table 5. IP bus mapping cross reference (continued)

Peripheral

STM32F0 series

STM32L0 series

Bus

Base address

Bus

Base address