Peripheral migration

AN4617

8/26

DocID027161 Rev 1

Note:

Yes++ = New feature or new architecture

Yes+ = Same feature, but specification change or design enhancement

Yes = Feature available

No = Feature not available

NA= Not applicable

2.2

System architecture

The STM32F0 MCU family has been designed to target an entry-level market, with low-

power capabilities and easy handling. To achieve this target and at the same time offer

coupled with minimal code footprint, results in low-cost applications with 32 bits

performance.

STM32L0 MCU family development goes in the similar way, one step further concerning

targeting application operating on battery or supplied by energy harvesting. Autonomous

peripherals capable to operate at low power mode reduce the core load and power

consumption.

in M0, two stages for M0+, both with maximum prefetch capacity up to two 16-bit

instructions. In addition, M0+ core features dedicated single cycle I/O port and memory

protection unit used by some L0 devices. A detailed comparison between these two cores

USB FS Device

Yes

Yes

SRAM partially shared with CAN

Identical

Full

Touch Sensing

Yes

Yes+

Dedicated IO pins

Identical for the same feature

Full

GPIO

Yes

Yes+

GPIO mapping and

configuration locking

Identical for the same feature

Full

CAN

Yes

No

NA

NA

NA

HDMI-CEC

Yes

No

NA

NA

NA

LCD

No

Yes

NA

NA

NA

AES

No

Yes

NA

NA

NA

RNG

No

Yes

NA

NA

NA

IRTIM

Yes

No

NA

NA

NA

Data EEPROM

No

Yes

NA

NA

NA

Table 4. STM32 peripheral compatibility analysis F0 versus L0 series (continued)

Peripheral

F0

series

L0

series

Compatibility

Possible differences

from user point of view

Pinout

FW driver

compatibility