Power supplies

AN4661

10/33

DocID027559 Rev 1

1.3

Reset & power supply supervisor

1.3.1

Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

1.8 V.

The device remains in reset mode when VDD/VDDA is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power-down reset threshold, refer to the electrical characteristics of the

datasheet.

Figure 2. Power on reset/power down reset waveform

1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge

is 1.70 V (typ.). Refer to STM32F756xx datasheets for the actual value.

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On the other packages, the power supply supervisor is always

enabled.

1.3.2

Programmable voltage detector (PVD)

The PVD can be used to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to

indicate if VDD is higher or lower than the PVD threshold. This event is internally connected

to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.

The PVD output interrupt can be generated when VDD drops below the PVD threshold

and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling

edge configuration. As an example the service routine could perform emergency shutdown

tasks.