AN4661 datasheet(12/33 Pages) STMICROELECTRONICS

12 / 33 page

Power supplies

AN4661

12/33

DocID027559 Rev 1

Figure 4. Power supply supervisor interconnection with internal reset OFF

When the internal reset is OFF, the following integrated features are no more supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

•

The brownout reset (BOR) circuitry must be disabled.

•

The embedded programmable voltage detector (PVD) is disabled.

•

VBAT functionality is no more available and VBAT pin should be connected to VDD.

All packages, except for the LQFP100, allow to disable the internal reset through the

PDR_ON signal when connected to VSS.

1.3.5

System reset

A system reset sets all registers to their reset values except the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 5).

A system reset is generated when one of the following events occurs:

A low level on the NRST pin (external reset).

Window watchdog end of count condition (WWDG reset).

Independent watchdog end of count condition (IWDG reset).

A software reset (SW reset) (see Software reset).

Low-power management reset (see Low-power management reset).

AN4661 Datasheet(PDF) 12 Page - STMicroelectronics