PIC16LC773-04SLASHSP datasheet(107/200 Pages) MICROCHIP

107 / 200 page

PIC16C77X

Advance Information

DS30275A-page 107

9.3

USART Synchronous Master Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner i.e. transmission and reception

do not occur at the same time. When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition enable bit SPEN (RCSTA<7>) is set in order to

configure the RC6/TX/CK and RC7/RX/DT I/O pins to

CK (clock) and DT (data) lines respectively. The Master

mode indicates that the processor transmits the master

clock on the CK line. The Master mode is entered by

setting bit CSRC (TXSTA<7>).

9.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 9-3. The heart of the transmitter is the transmit

(serial) shift register (TSR). The shift register obtains its

data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one Tcycle), the TXREG is empty and inter-

rupt bit, TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit TRMT (TXSTA<1>)

shows the status of the TSR register. TRMT is a read

only bit which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory so it is not

available to the user.

Steps to follow when setting up a Synchronous Master

Transmission:

Initialize the SPBRG register for the appropriate

baud rate (Section 9.1).

Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the

TXREG register.

TABLE 9-8

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all

other Resets

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN ADDEN

FERR

OERR

RX9D

0000 000x

19h

TXREG

USART Transmit Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.

Note 1:

Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

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