PIC16LC773-04SLASHSP datasheet(109/200 Pages) MICROCHIP

109 / 200 page

PIC16C77X

Advance Information

DS30275A-page 109

9.3.2

USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN (RCSTA<5>)

or enable bit CREN (RCSTA<4>). Data is sampled on

the RC7/RX/DT pin on the falling edge of the clock. If

enable bit SREN is set, then only a single word is

received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set

then CREN takes precedence.

Steps to follow when setting up a Synchronous Master

Reception:

Initialize the SPBRG register for the appropriate

baud rate. (Section 9.1)

Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

Ensure bits CREN and SREN are clear.

If interrupts are desired, then set enable bit

RCIE.

If 9-bit reception is desired, then set bit RX9.

If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

TABLE 9-9

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all

other Resets

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN ADDEN

FERR

OERR

RX9D

0000 000x

1Ah

RCREG USART Receive Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1:

Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

CREN bit

RC7/RX/DT pin

RC6/TX/CK pin

Write to

bit SREN

SREN bit

RCIF bit

(interrupt)

Read

RXREG

Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

'0'

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

'0'

Q1 Q2 Q3 Q4

PIC16LC773-04/SP Datasheet(PDF) 109 Page - Microchip Technology

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